Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow Embedded Resource Allocation

International audienceStream processing applications running on Heterogeneous Multi-Processor Systems on Chips (HMPSoCs) require efficient resource allocation and management, both at compile-time and at runtime. To cope with modern adaptive applications whose behavior can not be exhaustively predicted at compile-time, runtime managers must be able to take resource allocation decisions on-the-fly, with a minimum overhead on application performance. Resource allocation algorithms often rely on an internal modeling of an application. Directed Acyclic Graph (DAGs) are the most commonly used models for capturing control and data dependencies between tasks. DAGs are notably often used as an intermediate representation for deploying applications modeled with a dataflow Model of Computation (MoC) on HMPSoCs. Building such intermediate representation at runtime for massively parallel applications is costly both in terms of computation and memory overhead. In this paper, an intermediate representation of DAGs for resource allocation is presented. This new representation shows improved performance for run-time analysis of dataflow graphs with less overhead in both computation time and memory footprint. The performances of the proposed representation are evaluated on a set of computer vision and machine learning applications

Polynomial Approximation with Non-Uniform Segmentation for Bivariate Functions

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Constrain the Docile CTUs: an In-Frame Complexity Allocator for HEVC Intra Encoders

International audience—High Efficiency Video Coding (HEVC) is one of the latest released video standards and offers up to 40% bitrate savings when compared to the widespread H.264/AVC standard, at the cost of a substantial complexity growth. Constraining the complexity of HEVC encoding is a challenging task for embedded applications based on a software encoder. The most frequent approach to solve this problem is to optimise the coding tree structure to balance compression efficiency and computational complexity. In this context, we propose and assess a method to adequately allocate the computational complexity among coding units in a frame encoded in Intra mode. By studying an open-source real-time HEVC encoder, correlations are observed between Rate-Distortion (RD)-cost and encoding complexity that motivate a new complexity allocation technique. This technique, called " Constrain the Docile CTUs " (CDC), consists of allocating less computational complexity to units with low RD-costs and using RD-costs from preceding images as predictors for the current RD-costs. Experimental results demonstrate substantial gains, up to 36% of Bjøntegaard Delta Bit Rate (BD-BR), when using CDC method instead of other allocation methods

Machine Learning Based Choice of Characteristics for the One-Shot Determination of the HEVC Intra Coding Tree

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Prediction of quad-tree partitioning for budgeted energy HEVC encoding

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Energy Reduction Opportunities in an HEVC Real-Time Encoder

International audience—High Efficiency Video Coding (HEVC) is one of the latest released video standards and offers up to 40% bitrate savings when compared to the widespread H.264/AVC standard, at the cost of a substantial complexity growth. Constraining the complexity of HEVC encoding is a challenging task for embedded applications based on a software encoder. In the last few years, the Internet of Thingss (IoTs) has become a reality. Forecoming applications are likely to boost mobile video demand to an unprecedented level. In this context, designing energy-efficient HEVC real-time encoders is becoming a major challenge for software and hardware designers. In this paper, an analysis is conducted of the energy reduction opportunities offered by an HEVC encoder. The energy reduction search space is demonstrated, and the impact on energy consumption of encoding tools at various levels of granularity is measured

Delays and States in Dataflow Models of Computation

International audienceDataflow Models of Computation (MoCs) have proven efficient means for modeling computational aspects of Cyber-Physical System (CPS). Over the years, diverse MoCs have been proposed that offer trade-offs between expressivity, conciseness, predictability, and reconfigurability. While being efficient for modeling coarse grain data and task parallelism, state-of-the-art dataflow MoCs suffer from a lack of semantics to benefit from the lower grained parallelism offered by hierarchically modeled nested loops. In this paper 1 , a meta-model called State-Aware Dataflow (SAD) is proposed that enhances a dataflow MoC, introducing new semantics to take advantage of such nested loop parallelism. SAD extends the semantics of the targeted MoC with unambiguous data persistence scope. The extended expressiveness and conciseness brought by the SAD meta-model are demonstrated with a reinforcement learning use-case

PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPI

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On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion

International audienceFuture evolutions of the Internet of Things (IoT) are likely to boost mobile video demand to an unprecedented level. A large number of battery-powered systems will then integrate an High Efficiency Video Coding (Hevc) codec, implementing the latest video encoding standard from MPEG, and these systems will need to be energy efficient. Constraining the energy consumption of Hevc encoders is a challenging task, especially for embedded applications based on software encoders. The most efficient approach to manage the energy consumption of an Hevc encoder consists of optimizing the quad-tree partitioning and balance compression efficiency and energy consumption. The quad-tree partitioning splits the image into encoding units of variable sizes. The optimal size for a unit is content dependent and affects the encoding efficiency. Finding this optimal repartition is complex and the energy required by the so-called rate-distortion optimization (RDO) process dominates the encoder energy consumption. For the purpose of budgeting the energy consumption of a real-time Hevc encoder, we propose in this paper a variance-aware quad-tree prediction that limits the energetic cost of the RDO process. The predictor is moreover adjustable by two parameters, (Δ––,Δ¯¯¯¯), offering a trade-off between energetic gains and compression efficiency. Experimental results show that the proposed energy reduction scheme is able to reduce the energy consumption of a real-time Hevc encoder by 45–62% for a bit rate increase of, respectively, 0.49 and 3.4%. Moreover, the flexibility offered by parameters (Δ––,Δ¯¯¯¯) opens new opportunities for energy-aware encoding management

Probabilistic Approach Versus Machine Learning for One-Shot Quad-Tree Prediction in an Intra HEVC Encoder

International audienceEvolutions of the Internet of Things (IoT) in the next years are likely to boost mobile video demand to an unprecedented level. A large number of battery-powered systems will integrate an Hevc video codec, implementing the latest encoding MPEG standard, and these systems will need to be energy efficient. Constraining the energy consumption of Hevc encoders is a challenging task, especially for embedded applications based on software encoders. The most efficient approach to reduce the energy consumption of an Hevc encoder consists in optimizing the quad-tree block partitioning of the image and trade-off compression efficiency and energy consumption by efficiently choosing the near-optimal pixel block sizes. For the purpose of reducing the energy consumption of a real-time Hevc Intra encoder, this paper proposes and compares two methods that predict the quad-tree partitioning in “one-shot”, i.e. without iterating. These methods drastically limit the computational cost of the recursive Rate-Distortion Optimization (RDO) process. The first proposed method uses a Probabilistic approach whereas the second method is based on Machine Learning approach. Experimental results show that both methods are capable of reducing the energy consumption of an embedded Hevc encoder of 58% for a bit rate increase of respectively 3.93% and 3.6%